Compact and Scalable Multiple-Input Multiple-Output Systems for Future 5G Networks The proposed 28GHz beamformer shares radio frequency elements for the highest area efficiency among multiple-input multiple-output receivers

A 28GHz time-division multiple-input multiple-output (MIMO) receiver with eight radio frequency elements, each occupying just 0.1 mm², has been developed by researchers at Tokyo Tech using 65nm CMOS technology. This innovative design reduces chip size for beamforming. Achieving -23.5 dB error vector magnitude in 64-quadrature amplitude modulation and data rates up to 9.6 Gbps, this receiver offers the highest area efficiency and fastest beam switching among reported MIMO receivers.

To meet the growing need for data from applications like video streaming, augmented reality, autonomous vehicles, and Internet of Things devices, 5G New Radio and future beyond 5G technologies utilize multi-beam multiple-input multiple-output to send and receive multiple streams of data simultaneously. An essential component for effective MIMO operation is beamforming. Beamforming adjusts the signals to focus them towards the transmitters or receivers. This process improves signal quality and minimizes interference. However, conventional analog beamforming MIMO receivers require separate beamformers for each data stream, making it challenging to implement in a millimeter wave MIMO system like a 28GHz MIMO transceiver where the antenna pitch (the distance between antennas) is only 5 millimeters.

To address this, researchers led by Professor Kenichi Okada from Tokyo Institute of Technology have proposed a novel technique called time-division MIMO (TD-MIMO) beamformer that can support millimeter-wave MIMO without the need for additional hardware. The study has been published in the Proceedings of the 2024 IEEE VLSI Symposium and presented at the 2024 IEEE Symposium on VLSI Technology & Circuits, June 16-20 in Honolulu, USA.

"The major challenge with conventional millimeter-wave MIMO receivers is that their area and power consumption increase linearly with the number of MIMO streams they need to support. As a result, the chip size scales with the number of MIMO streams. Therefore, more than three MIMO streams have never been demonstrated for a 2D array," explains Okada.

In MIMO systems, each antenna connects with every other antenna via a network of radio frequency (RF) paths. The number of these paths is determined by multiplying the number of MIMO streams by the number of antennas. Therefore, increasing the number of data streams increases the RF paths needed.

In TD-MIMO operation, an analog beamformer quickly switches the beam pattern or direction of the receiver at very high speeds, allowing multiple signals to use the same RF paths. After the beamforming process, a TD-MIMO switch directs each MIMO stream to separate output ports, ensuring that the signals do not interfere with each other.

This system uses fast-switching phase shifters which can adjust the signal phase within 2.5 nanoseconds, and clock-based synchronization to control the timing of the beam switching. This approach enables the TD-MIMO receiver to support more data streams by simply increasing the clock frequency, ensuring scalable data transmission without increasing the size of the chipset.

Researchers developed a 3mm x 2mm TD-MIMO receiver using 65nm CMOS technology consisting of 8 RF elements to handle four separate 5G New Radio data streams across a 400MHz channel bandwidth using 64-quadrature amplitude modulation (QAM). The signals pass through a Wilkinson power combiner to a TD-MIMO switch, which separates them into four paths. Each RF element features a noise-cancelling amplifier and a fast phase shifter. A variable gain amplifier and a retiming circuit keep the system in sync by ensuring the switching occurs accurately (refer to Figures 1 and 2).

A 3-stage 8-to-1 Wilkinson power combiner combines the beams, which are then separated to respective outputs by a TD-MIMO switch. An H-tree network distributes the synchronization clock to each receiver element, with DTCs in the clock distribution network for precise timing calibration.

The TD-MIMO receiver is fabricated using a common 65nm CMOS process making it suitable for scalable production. The PCB has four layers and integrates a 1 by 8 antenna array in the bottom layer.

The receiver successfully handled 5G-compliant MIMO signals from a Keysight arbitrary waveform generator transmitted by horn antennas in four directions. It achieved -23.5 dB error vector magnitude in 64-QAM and a rapid Nyquist-rate beam switching time of 0.15 ns, enabling data rates up to 9.6 Gbps across the four-stream MIMO configuration.

"This work realizes highest data rates with highest area efficiency among listed MIMO receivers," says Okada. With each RF element occupying just 0.1 mm², the proposed chipset can pave the way to smaller and more compact efficient, scalable, multi-beam MIMO systems for high-speed data transmission.

This work is partially supported by the National Institute of Information and Communications Technology (NICT) in Japan (JPJ012368C00801).